1. Field of the Invention
The present invention relates to a plasma display panel, and more particularly, to a driving method of a plasma display panel for improving a picture quality.
2. Description of the Related Art
Plasma display panel (hereinafter referred to as “PDP”) generally displays an image including character or graphic by generating light from fluorescent substance using ultraviolet rays with a wavelength of 147 nm, which is generated during a gas LB discharge of an inert mixture gas, such as He+Xe, Ne+Xe, He+Ne+Xe or the like. This PDP has easy slimness and large-sized characteristics, and provides a greatly improved picture quality thanks to the recent technology development. Especially, three-electrode alternating current (AC) surface discharge type PDP has advantages of a low voltage operation and a long life since wall charges stored on a surface in the course of discharge protect electrodes from sputtering generated by the discharge.
FIG. 1 is a view illustrating a discharge cell of a conventional three-electrode AC surface discharge type plasma display panel.
Referring to FIG. 1, a discharge cell of the three-electrode AC surface discharge type PDP includes a scan electrode (Y) and a sustain electrode (Z) formed on an upper substrate 10, and an address electrode (X) formed on a lower substrate 18. Each of the scan electrode (Y) and the sustain electrode (Z) includes transparent electrodes 12Y and 12Z and metal bus electrodes 13Y and 13Z having line widths narrower than line widths of the transparent electrodes 12Y and 12Z formed at one-sided edge regions of the transparent electrodes 12Y and 12Z.
The transparent electrodes 12Y and 12Z are generally formed of Indium-Tin-Oxide (hereinafter, referred to as ‘ITO’) on the upper substrate 10. The metal bus electrodes 13Y and 13Z are generally formed of chrome (Cr) on the transparent electrodes 12Y and 12Z to function to reduce a voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. An upper dielectric layer 14 and a passivation film 16 are layered on the upper substrate 10 having the scan electrode (Y) and the sustain electrode (Z) formed in parallel with each other. The wall charge generated at the time of plasma discharge is stored in the upper dielectric layer 14. The passivation film 16 prevents the upper dielectric layer 14 from being damaged due to the sputtering generating at the time of the plasma discharge and also, enhances an emission efficiency of a secondary electron. Magnesium oxide (Mgo) is generally used as the passivation film 16. A lower dielectric layer 22 and a barrier 24 are formed on the lower substrate 18 having the address electrode (X), and a fluorescent layer 26 is coated on a surface of the lower dielectric layer 22 and the barrier 24. The address electrode (X) is formed in a direction of crossing with the scan electrode (Y) and the sustain electrode (Z). The barrier 24 is formed in parallel with the address electrode (X) to prevent the visible ray and the ultraviolet ray caused by the discharge from being leaked to an adjacent discharge cell. The fluorescent layer 26 is excited by the ultraviolet ray generated due to the plasma discharge to radiate any one visible ray of red, green or blue. The inert mixture gas for the discharge such as He+Xe, Ne+Xe, He+Ne+Xe and the like is injected into a discharge space of the discharge cell provided between the upper/lower substrates 10 and 18 and the barrier 24.
In the above three-electrode AC surface discharge type PDP, one frame is divided into several sub-fields having different times of light-emitting (for example, the number of a sustain pulse) so as to realize a gray level of the image. Each of the sub-fields is again divided into a reset period during which the discharge is uniformly generated, an address period during which the discharge cell is selected, and the sustain period during which the gray level is embodied depending on discharge times. For example, in case that the image is expressed using a 256 gray level as in FIG. 2, a frame period (16.67 ms) corresponding to 1/60 second is divided into eight sub-fields (SF1 to SF8). Also, each of the eight sub-fields (SF1 to SF8) is again divided into a reset period, an address period and a sustain period. Herein, the reset and address periods of each sub-field are identical every sub-field, whileas the sustain period is increased in a ratio of 2n (n=0, 1, 2, 3, 4, 5, 6, 7) at each of the sub-fields. As described above, brightness weighting values different from one another every sub-field are combined to embody a certain gray level.
On the other hand, the conventional PDP can control the number of the sustain pulse depending on an Average Picture Level (hereinafter, referred to as “APL”) such that a consumption power can be constantly processed.
FIG. 3 is a general graph illustrating the number of the sustain pulse depending on the APL.
Referring to FIG. 3, since brightness is determined depending on the number of the sustain pulse, if a total number of the sustain pulse is made identical in cases that an average brightness is dark and bright, the PDP has several drawbacks of a picture quality deterioration, a power consumption, a panel damage and the like. For example, a contrast is decreased in case that the number of the sustain pulse is set to be small for all inputted images. Further, in case that the number of the sustain pulse is set to be large for all inputted images, the PDP has an advantage in that the brightness is bright and the contrast is increased even at a dark image, but the panel can be damaged due to an increased consumption power and an elevated temperature of the panel. Accordingly, it is required to properly adjust the total number of the sustain pulse depending on the average brightness of the inputted image. Herein, the number of the sustain pulse is abruptly increased in a range of gray level having a relative low APL, and is decreased in a range of gray level having a relative high APL. Accordingly, the number of the sustain pulse is abruptly varied in the range of gray level having the relative low APL.
FIG. 4 is a view illustrating a voltage waveform representing a conventional driving method of the PDP.
Referring to FIG. 4, the sub-field (SF) included in one frame of the PDP is divided for an operation into the reset period (RPD), the address period (APD) and the sustain period (SPD).
A reset pulse (RP) is supplied to the scan electrode (Y) during the reset period (RPD). The reset pulse (RP) having a ramp wave format is in a way of increasing voltage during a set-up period and decreasing the voltage during a set-down period. In the set-up period during which the voltage is gradually increased, a plurality of minute set-up discharges is generated to form the wall charge in the upper dielectric layer. Continuously, in the set-down period during which the voltage is gradually decreased, unnecessary charged particles are partially removed due to a plurality of minute set-down charges such that the wall charge is decreased as much as a next address discharge is helped without an erroneous discharge. A positive-polar (+) direct-current voltage is supplied to the sustain electrode (Z) during the set-down period. Since the reset pulse (RP) is supplied gradually attenuating with respect to the positive-polar (+) direct-current voltage, the scan electrode (Y) has a relative negative polarity (−) with respect to the sustain electrode (Z), that is, polarity is inverted at the time of set-down thereby causing the wall charges generated at the time of set-up to be decreased.
During the address period (APD), a scan pulse (SP) having a negative-polar (−) scan voltage (Vy) is supplied to the scan electrode (Y) and at the same time, a positive-polar (+) data pulse (DP) is supplied to the address electrode (x) thereby causing the address discharge. The wall charge formed due to the address discharge is maintained during a period during which other discharge cells are addressed.
During the sustain period (SPD), a triggering pulse (TP) is supplied to the scan electrode (Y) such that a sustain discharge is initiated at the discharge cells where enough wall charges are formed during the address period (APD). Next, sustain pulses (SUSPz and SUSPy) corresponding to the sustain voltage (Vs) are alternatively supplied to the sustain electrode. (Z) and the scan electrode (Y) such that the sustain discharge is maintained during the sustain period (SPD)
During an erase period (EPD) following the sustain period (SPD), an erase pulse (EP) is supplied to the sustain electrode (Z) thereby stopping the maintained discharge. The erase pulse has the ramp wave format to provide small-sized light-emitting, or a short pulse width of about 1 μs for a discharge erase. The charged particles are erased using a short erase discharge caused by the erase pulse (EP), to thereby stop the discharge.
On the other hand, in the conventional art, the reset period (RPD) and the address period (APD) are identical every sub-field within one frame, whileas the sustain period (SPD) is increased in the ratio of 2n (n=0, 1, 2, 3, 4, 5, 6, 7) at each of the sub-fields. Since the sustain period (SPD) is different at each of the sub-fields as described above, the gray level of LB the image can be embodied. However, since the frames are identically arranged every vertical synchronous signal as in FIG. 5, the gray level is limitedly expressed. In FIG. 5, the number of the sub-field is 12, and the number of the sub-field can be variously varied depending on the gray level to be embodied.
Accordingly, in order to overcome a limitation in expressing the gray level, it has been proposed that two frames of FIGS. 6A and 6B be alternatively arranged every vertical synchronous signal. For example, the sub-fields are arranged at an odd frame (or an even frame) in a weighted value ratio of 1, 6, 13, 23, 35, 51, 70, 91, 116, 145, 176 and 211 as in FIG. 6A, and the sub-fields are arranged at the even frame (or the odd frame) in a weighted value ratio of 4, 9, 18, 29, 43, 60, 80, 103, 130, 160, 193 and 109 as in FIG. 6B. In case that the odd frame and the even frame having the different brightness weighting value of each sub-field are alternatively used every vertical synchronous signal (Vsync), an expression degree of the gray level can be increased at least twice as much as the case where the frames having the same brightness weighting value of each sub-field are arranged. At this time, the brightness weighting values of the sub-field should be set to be alternated each other every-frame.
For example, the brightness weighting values of the odd frame and the even frame can be set to be alternated such as 1, 4, 6, 9, 13, 18, 23, 29 and the like.
However, in case that the brightness weighting value is alternatively arranged every frame as described above, there is a drawback in that light-emitting centers of each frame are inconsistent, and a flicker is generated to an extent of being unpleasant to the eye thereby deteriorating the picture quality.
That is, when all sub-fields of each frame are turned-on, a light-emitting center of an odd numbered frame is a 211 position of the brightness weighting value, whileas a light-emitting center of an even numbered frame is a 193 position of the brightness weighting value. Accordingly, the positions of the light-emitting centers of both frames are different from each other thereby causing the flicker and accordingly, critically influencing the picture quality.
Describing this in detail, in case that two frames having different brightness weighting values are alternatively arranged, a vertical frame blank (hereinafter, referred to as “VFB”) period between an nth frame (n) and a (n+1)th frame (n+1) becomes T1, and a VFB between the (n+1)th frame (n+1) and a (n+2)th frame (n+2) becomes T1 as in FIG. 6C. As illustrated in FIG. 6C, it can be understood that T2 is longer than T1. Further, BFBs between the frames are alternatively arranged. At this time, since T1 and T2 are different from each other, the light-emitting centers of respective frames are inconsistent to cause the flicker to the extent of being unpleasant to the eye thereby deteriorating the picture quality.
On the other hand, a selective write and selective erase (SWSE) driving method has been proposed for reinforcing the expression degree of the gray level. In the above selective write and selective erase driving method, one frame is comprised of at least one selective write sub-field and at least one selective erase sub-field.
FIG. 7 is a view illustrating a waveform representing a conventional driving method of a selective write and selective erase PDP driven in a 60 Hz mode.
Referring to FIG. 7, one frame of the selective write and selective erase PDP is comprised of at least one selective write sub-field and at least one selective erase sub-field. At this time, the at least one selective write sub-field can be a selective write duration (SW6 and the like), and the at least one selective erase sub-field can be a selective erase duration (SE1, SE2 and the like).
Further, the selective write sub-field is divided into a reset period (IPD), an address period (APD), and a sustain period (SPD), and the selective erase sub-field is divided into an address period (APD) and a sustain period (SPD).
Describing this in detail, a set-down waveform ramp pulse (-RP) is sequentially supplied during the reset period (RPD) of the selective write sub-field to scan electrode lines (Y) following a set-up waveform reset pulse (RP). The set-down waveform ramp pulse (−RP) drops to a negative-polar (−) scan reference voltage (−Vw). Further, a positive-polar (+) direct-current voltage is supplied to sustain electrode lines (Z)
While the positive-polar (+) direct-current voltage is supplied to the sustain electrode lines (Z) during the address period (APD) of the selective write sub-field, a negative-polar (−) selective write scan pulse (SWSP) and a positive-polar (+) selective write data pulse (SWDP) are supplied to each of the scan electrode lines (Y) and the address electrode lines (X) to be synchronized with each other. Continuously, sustain pulses (SUSPy and SUSPz) are alternatively supplied to the scan electrode lines (Y) and the sustain electrode lines (Z) such that the sustain discharge is generated at a cell turned-on by the address discharge of the selective write sub-field during the sustain period (SPD) of the selective write sub-field.
The reset period (RPD) of the selective erase sub-field is omitted. During the address period (APD) of the selective erase sub-field, a negative-polar (−) selective erase scan pulse (SESP) and a positive-polar (+) selective erase data pulse (SEDP) are supplied to each of the scan electrode lines (Y) and the address electrode lines (X) to be synchronized with each other. The selective erase scan pulse (SESP) drops to a negative-polar (−) selective erase scan voltage (Ve) higher than the negative-polar (−) scan reference voltage (Vw).
The sustain pulses (SUSPy and SUSPz) are alternatively supplied to the scan electrode lines (Y) and the sustain electrode lines (Z) such that the sustain discharge is generated at cells not turned-off by the address discharge of the selective erase sub-field (ESF) during the sustain period (SPD) of the selective erase sub-field. In case that a next following sub-field is the selective erase sub-field, the sustain pulse (SUSPy) having a relatively large pulse width is supplied to the scan electrode lines (Y) at the end time of a present selective erase sub-field. Additionally, an erase pulse (not shown) and a ramp signal (not shown) are supplied to the scan electrode lines (Y) and the sustain electrode lines (z) at the last selective erase sub-field having the selective write sub-field as the next sub-field to erase the sustain discharge of the turned-on cells.
FIG. 8 is a view illustrating an example of a sub-field arrangement where the gray level is expressed in a selective write and selective erase way of FIG. 7.
Referring to FIG. 8, in order to express the gray level, the sub-field from a low gray level to a first 32 gray level is addressed in a selective write way, and remaining sub-fields are addressed in a selective erase way. At this time, in case that a 50 Hz driving is performed using the selective write and selective erase way, the flicker is caused by a phenomenon of a relative VFB increase (that is, VFB*(vertical frame blank at the time of a 60 Hz driving)<VFB** (vertical frame blank at the time of the 50 Hz driving)). The above flicker is an obstacle in the picture quality. Describing this in detail, in case that it is intended to display the-image, South Korea and United Stated America use the 60 Hz mode, that is, the frame period (16.67 ms) corresponding 1/60 second. However, Europe, China and the like use a 50 Hz mode, that is, a frame period (20 ms) corresponding to 1/50 second. At this time, in case that one frame period is 60 Hz, the VFB period is VFB*. However, in case that a signal of the 60 Hz mode is applied to the 50 Hz mode, the VFB period is VFB** longer than the case of 60 Hz. Accordingly, since the VFB* period of the 60 Hz mode is short and the VFB** period of the 50 Hz mode is long, in case that the frame of the 60 Hz mode is applied to the 50 Hz mode, there is a drawback in that since the VFB period is lengthened thereby causing the phenomenon of inconsistency of the light-emitting centers, the flicker is caused thereby deteriorating the brightness.